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Appendix C: LCD Interface
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The voltage follower and voltage regulator are set to:
R
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Five times boost mode
The V4, V3, V2, V1, and V0 outputs depend on the bias settings of 1/9 or 1/7.
Because of these default settings, the following display controller connections are not used:
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DISP: Turns into an output when Master mode is selected
FRS: Static driver segment output
M: Used in Master/Slave display configurations
CL: Clock pin used in Master/Slave display configurations
When RESETB is Low, the display controller is initialized as indicated in Table C-3 .
Table C-3:
Display Controller Initialization (RESETB is Low)
Parameter
Display
Entire Display
ADC Select
Reverse Display
Power Control
LCD Bias
Read-Modify-Write
SHL Select
Static Indicator Mode
Static Indicator Register
Display Start
Column Address
Page Address
Regulator Select
Reference Voltage
Reference Voltage Register
Initial Value
OFF
OFF
OFF
OFF
0,0,0 (VC, VR, VF)
1/7
OFF
OFF
OFF
0,0 (S1, S0)
0 (First line)
0
0
0,0,0 (R2, R1, R0)
OFF
1,0,0,0,0,0 (SV5, SV4, SV3, SV2, SV1, SV0)
When RESETB is High, the display must be initialized. The first steps to be taken to
guarantee correct operation of the display and the controller are:
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Configure the ADC bit. This bit determines the scanning direction of the segments.
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When the RESETB signal is active, ADC is reset to 0 , meaning that the segments
are scanned from SEG1 up to SEG132.
When ADC is set to 1 , the segments are scanned in opposite direction.
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Configure the SHL bit. This bit sets the scanning direction of the COM lines.
?
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When the RESETB signal is active, SHL is reset to 0 , meaning that the segments
are scanned from COM1 up to COM64.
When SHL is set to 1 , the common lines are scanned in opposite direction.
128
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Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
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